1. Field of the Invention
The present invention relates to a solid-state imaging device including an amplification-type MOS transistor and a method of manufacturing the same.
2. Related Background Art
In recent years, attention has been drawn to a solid-state imaging device including an amplification-type MOS transistor. In such a solid-state imaging device, for each pixel, a signal detected by a photodiode is amplified by a MOS transistor, and the device is characterized by its high sensitivity.
FIG. 10 is a circuit diagram showing a configuration of a conventional solid-state imaging device 90. The solid-state imaging device 90 includes a plurality of pixel cells 96 laid out in matrix form on a semiconductor substrate 7. Each of the pixel cells 96 includes a photodiode 3 that converts incident light into a signal charge and stores the signal charge. In each of the pixel cells 96, a transfer transistor 4 for reading out the signal charge stored in the photodiode 3 is provided.
Each of the pixel cells 96 includes an amplify transistor 14. The amplify transistor 14 amplifies the signal charge read out by the transfer transistor 4. In each of the pixel cells 96, a reset transistor 15 is provided. The reset transistor 15 resets the signal charge read out by the transfer transistor 4.
The solid-state imaging device 90 includes a vertical driving circuit 12. A plurality of reset transistor control lines 111 are connected to the vertical driving circuit 12. The reset transistor control lines 111 are arranged at a predetermined distance from and parallel to each other along a horizontal direction so as to be connected respectively to the reset transistors 15 that are provided respectively in the pixel cells 96 laid out along the horizontal direction. A plurality of vertical select transistor control lines 121 further are connected to the vertical driving circuit 12. The vertical select transistor control lines 121 are arranged at a predetermined distance from and parallel to each other along the horizontal direction so as to be connected respectively to vertical select transistors 16 that are provided respectively in the pixel cells 96 laid out along the horizontal direction. The vertical select transistor control lines 121 determine from which row signals are to be read out.
The respective sources of the vertical select transistors 16 are connected to vertical signal lines 61. A load transistor group 17 is connected to one end of each of the vertical signal lines 61. The other end of each of the vertical signal lines 61 is connected to a row signal storing part 18. The row signal storing part 18 includes a switching transistor for capturing signals to be obtained from one row. A horizontal driving circuit 13 is connected to the row signal storing part 18.
FIG. 11 is a timing chart for explaining an operation of the conventional solid-state imaging device 90.
When a row selection pulse 101-1 for increasing the power level of the vertical select transistor control line 121 is applied, the vertical select transistors 16 in a selected row are activated, so that the amplify transistors 14 in the selected row and the load transistor group 17 form a source follower circuit.
While the row selection pulse 101-1 is at a high level, a reset pulse 102-1 for increasing the power level of the reset transistor control line 111 is applied so as to reset a potential of a floating diffusion layer to which a gate of each of the amplify transistors 14 is connected. Then, while the row selection pulse 101-1 is at a high level, a transfer pulse 103-1 is applied so as to increase the power level of a transfer transistor control line. This allows a signal charge stored in each of the photodiodes 3 to be transferred to the floating diffusion layer.
At this time, the amplify transistors 14 connected to the floating diffusion layer have a gate voltage equal to the potential of the floating diffusion layer. A voltage that is substantially equal to this gate voltage appears at the vertical signal lines 61. Then, a signal based on the signal charge stored in each of the photodiodes 3 is transferred to the row signal storing part 18.
Next, the horizontal driving circuit 13 generates a column selection pulses 106-1-1, 106-1-2, . . . one after another and extracts the signals that have been transferred to the row signal storing part 18 as an output signal 107-1 corresponding to the signals obtained from one row.
FIG. 12 is a plan view for explaining a configuration of the photodiode 3 and the transfer transistor 4 that are provided in the pixel cell 96 of the conventional solid-state imaging device 90. FIG. 13 is a cross sectional view taken along a plane PP shown in FIG. 12.
Between the photodiode 3 and the transfer transistor 4, an element isolating portion 92 formed of a STI (Shallow Trench Isolation) that is a grooved portion of the semiconductor substrate 7 is formed so that the photodiode 3 and the transfer transistor 4 are isolated from each other.
The transfer transistor 4 includes gate electrodes 53 formed on the semiconductor substrate 7 and source/drain regions 5, each of which is formed on a surface of the semiconductor substrate 7 on each side of the respective gate electrodes 53.
An element isolating portion 92A is formed so that the photodiode 3 is isolated from another photodiode 3 contained in the pixel cell 96 adjacent to the pixel cell 96 containing the photodiode 3.
FIG. 14 is a cross sectional view for explaining a configuration of the element isolating portion 92. FIG. 15 is a graph showing a defect density obtained along a plane XY shown in FIG. 14. FIG. 16 is schematic sectional view for explaining a configuration of the element isolating portion 92 and the photodiode 3.
The photodiode 3 is an embedded photodiode in which a p+ layer 8, an n layer 9 and a p layer 10 are formed in this order starting from a surface side of the semiconductor substrate 7.
One of the reasons for the poor performance of MOS type sensors is that a reverse-direction leakage current 89 flows from the element isolating portion 92 to the photodiode 3 in which a pn junction is established between the p+ layer 8, the n layer 9 and the p layer 10. This reverse-direction leakage current is increased due to a crystal defect and stress caused in the semiconductor substrate 7.
It has been revealed that in the structure of a MOS transistor, a crystal defect and stress are most likely to be caused by the element isolating portions 92 and 92A.
As such a crystal defect, conventionally, a crystal defect 52 that is caused at a corner of the surface of the semiconductor substrate 7 in the vicinity of the element isolating portion 92 has been well known. Further, a crystal defect 53 that is caused on a lower side of the element isolating portion 92 recently has been viewed as a problem.
The crystal defect 52 and the crystal defect 53 as described above have a large size of about not less than 0.5 μm. These defects cause the performance of a MOS transistor to be deteriorated and thus, while being suppressed by annealing or the like in a heating process, have remained as major problems.
As shown in FIG. 15, an interface between the element isolating portion 92 and the semiconductor substrate 7 was analyzed in detail along a cross section XY shown in FIG. 14. The results of the analysis revealed that small defects caused due to the crystal defect 52 and the crystal defect 53 were distributed. These defects are extremely small and thus present no problem in the conventional MOS transistors.
In FIG. 15 as closely seen, an interface defect layer 94 and a STI stress defect layer 95 are observed. The interface defect layer 94 has been well known conventionally and is present in a place that is in contact with the interface between the element isolating portion 92 and the semiconductor substrate 7. The STI stress defect layer 95 is formed conceivably due to stress caused by a STI. Unlike the crystal defect 52 and the crystal defect 53 that are caused locally at ends of a STI due to the above-mentioned stress caused by the STI, the STI stress defect layers 95 are distributed near the interface between the element isolating portion 92 and the semiconductor substrate 7.
The crystal defect 52 and the crystal defect 53 are not necessarily caused at ends of a STI but caused such that these defects, which are several in number, are distributed in a semiconductor chip. In a semiconductor substrate, stress exerted around these defects caused therein is released, resulting even in a phenomenon in which the STI stress defect layer 95 is decreased in size. The cause and effect of this phenomenon is yet to be analyzed definitely, and there are even cases where the phenomenon cannot be observed definitely. The STI stress defect layer 95, while its size may vary, is caused in a place at a distance from the interface of about 0.01 μm, and even at a distance of 0.02 μm when the bottom of the distribution is considered.
In a MOS type solid-state imaging device in which the above-mentioned STI element isolating portions 2 and 2A are provided, the crystal defect 52 and the crystal defect 53 appear on a reproducing screen in the form of several to several thousands of white point defects with large output. The number of such point defects varies depending on how a STI has been formed and the scale of the imaging device.
The STI stress defect layer 95 causes the reverse leakage current 89 to be generated and is observed as small and uneven variations on the reproducing screen.
The conventional problem has been the former, i.e. point defects originating in the crystal defect 52 and the crystal defect 53, which are caused locally. With the recent advances of the digital technologies, it has been possible to correct white flaws originating in the crystal defect 52 and the crystal defect 53 that are caused in small numbers, and thus such point defects no longer have been a serious problem.
However, in order to correct small and uneven variations originating in the STI stress defect layer 95, a large-capacity memory is required to correct the variations caused over the entire screen. This requires a costly system for the correction, which has been disadvantageous.
It is an object of the present invention to provide a high-performance solid-state imaging device that achieves a reduction in variations appearing on a reproducing screen and a method of manufacturing the same.